The PLUS Accelerator 
Roberto Bisiani, Principal Investigator 
School of Computer Science 
Carnegie Mellon University 
Pittsburgh, PA 15213 
Our plan is to demonstrate a workstation accelerator 
(called PLUS) that not only executes the current speech 
recognition systems in real time, but that will also support 
the increasing computational demands of speech recog- 
nition systems in the next several years. The accelerator 
will also be useful for other compute-bound applications. 
The accelerator will be replicated and made available to 
other sites. 
Our approach is to connect single-processor machines of 
roughly the performance of high-end workstations by 
means of a very fast and powerful communication 
mechanism. This makes the memory on each node visible 
to every other node as if the system were a single shared- 
memory multiprocessor. The prototype, for example, uses 
25MHz Motorola 88000 processors with up to 32 Mbytes 
of DRAM memory and 512 Kbytes of SRAM in each 
node; the interconnection is based on a MOSIS-built mesh 
router with 40Mbytes/sec bandwidth. 
PLUS research contribution comprises new mechanisms 
to support shared-memory and synchronization between 
processors. The emphasis is on low latency and low over- 
head synchronization. 
The PLUS prototype is interfaced to host computer sys- 
tems by means of a SCSI interface, this interface can also 
perform speech input/output and limited signal processing. 
Interfacing PLUS to a host does not require any operating 
system change on the host. 
We have completed the design of both the PLUS board 
and of the host interface. After fabrication i s completed we 
expect to take about two months for debugging and then 
start replication. Minimal software (sufficient, for example, 
for running the Sphinx system) is already available. 
Motivation and description of the PLUS architecture can 
be found in: 
Bisiani, R. and Ravishankar, M. 
Programming the PLUS Distributed-Memory System 
Fifth Distributed Memory Computing Conference 
Charleston, SC, April 1990 
Bisiani, R. and Ravishankar, M. 
PLUS: A Distributed Shared Memory System 
17th Annual International Symposium on 
Computer Architecture 
Seattle, WA, May 1990 
This project is co-sponsored by Apple Computer, Inc. 
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