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<Paper uid="P90-1039">
  <Title>A HARDWARE ALGORITHM FOR HIGH SPEED MORPHEME EXTRACTION AND ITS IMPLEMENTATION</Title>
  <Section position="3" start_page="0" end_page="0" type="intro">
    <SectionTitle>
1 INTRODUCTION
</SectionTitle>
    <Paragraph position="0"> Recent advancement in natural language parsing technology has especially extended the word processor market and the machine translation system market. For further market extension or new market creation for natural language applications, parsing speed-up as well as improving parmng accuracy is required. First, the parsing speed-up directly reduces system response time required in such interactive natural language application systems as those using natural language interface, speech recognition, Kana-to-Kanjl i conversion, which is the most popular Japanese text input method, and so on. Second, it also increases the advantage of such applications as machine translation, document proofreading, automatic indexing, and so on, which are used to treat a large amount of documents. Third, it realizes parsing methods based on larger scale dictionary or knowledge database, which are necessary to improve parsing accuracy.</Paragraph>
    <Paragraph position="1"> Until now, in the natural language processing field, the speed-up has depended mainly on performance improvements achieved in sequential processlng computers and the development of sequential algorithms. Recently, because of the further IKan~ characters are combined consonant and vowel symbols used in written Japanese. Kanjl characters ~re Chinese ideographs.</Paragraph>
    <Paragraph position="2"> speeded-up requirement, parallel processing computers have been designed and parallel parsing algorithms (Matsumoto, 1986) (Haas, 1987) (Rytter, 1987) -(Fukushima, 1990b) have been proposed. However, there are many difficult problems blocking efficient practical use of parallel processing computers. One of the problems is that access confiicts occur when several processors read or write a common memory simultaneously. Another is the bottle-neck problem, wherein commtnication between any two processors is restricted, because of hardware scale limitation.</Paragraph>
    <Paragraph position="3"> On the other hand, in the pattern processing field, various kinds of accelerator hardware have been developed. They are designed for a special purpose, not for general purposes. A hardware approach hasn't been tried in the natural language processing field yet.</Paragraph>
    <Paragraph position="4"> The authors propose developing natural language parsing accelerators, a hardware approach to the parsing speed-up (Fukushima, 1989b) -(Fukushima, 1990a). This paper describes a new hardware algorithm for high speed morpheme extraction and its implementation on a specific machine. This morpheme extraction machine is designed as the first step toward achieving the natura\] language parsing accelerators.</Paragraph>
  </Section>
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