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<Paper uid="H90-1018">
  <Title>Hardware for Hidden Markov-Model-Based, Large-Vocabulary Real-Time Speech Recognition</Title>
  <Section position="4" start_page="85" end_page="86" type="metho">
    <SectionTitle>
3 Implementation
</SectionTitle>
    <Paragraph position="0"> All the memories on the system are accessible by the host CPU via VME bus. To reduce the number of discrete components on the system, the host CPU communicates only to the custom VLSI processors. These processors have a small instruction set to read and write memories and internal status registers.</Paragraph>
    <Paragraph position="1"> Using this approach, no address or data bus has to be multiplexed.</Paragraph>
    <Paragraph position="2"> The testing strategy for the custom processors is scanpath testing. Individual chips can be tested by using a generic scantest setup, or they can be tested on the board by using the existing VME interface. A dedicated onchip test controller supervises this VME test mode so that even the VME interface controller can be tested. This way, every state on the complete board (except the test controller itself) is observuble and controllable without a change of hardware.</Paragraph>
    <Paragraph position="3"> The board has two copies of six generic VLSI processors that implement the ToActiveWord and Viterbi processes. The chips were designed with the Berkeley LagerIV silicon assembly system \[2\] and are currently under fabrication using a 2-#m CMOS technology. The table below summarizes the statistics for the processors.</Paragraph>
  </Section>
  <Section position="5" start_page="86" end_page="86" type="metho">
    <SectionTitle>
4 Status and future work
</SectionTitle>
    <Paragraph position="0"> All the chips listed have been designed and verified. They are currently being fabricated through MOSIS using a 2-#m CMOS process. We have received some of the chips back, and are currently testing them and building the two custom boards. After completing the construction of the current hardware design, we will be developing software tools to support this architecture, and to run recognition experiments and real-time systems. null Once we have completed the construction of the first system, we will evaluate the current architecture to determine the computational and algorithmic bottlenecks. To fully use the capabilities of this design we will be developing a large vocabulary recognizer to run on this board. A major area of research will be the design and implementation of algorithms for real-time grammar processing computation, since these parts of the system will be running on general-purpose CPUs (TMS320C30s communicating with SUNs).</Paragraph>
    <Paragraph position="1"> recognition for large vocabularies in real time. The system will be at least by a factor of 50 more powerful than existing solutions.</Paragraph>
  </Section>
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